This invention relates to DRAM(Dynamic Random Access Memory) cells and a method for manufacturing them, and more particularly to a stacked capacitor DRAM cell which can obtain a high-capacitance without the increment of capacitor area in a semiconductor device. Recently, in the field of DRAM technology, the effort of minimizing the chip size has been completed, while the capacitance value needed for each cell has been maintained. According to such trend, the trench capacitor DRAM cell and stacked capacitor DRAM cell came on. These techniques contributed largely to the high-density DRAM technology.
To explain the method for manufacturing a stacked capacitor DRAM cell, referring to FIG. 1 which shows the vertical cross-sectional view of a stacked capacitor DRAM cell, the fabricating processes of the stacked capacitor DRAM cell are as follows.
At first, a p-well 32 is formed on a p-type substrate 31. A field oxide 34 is grown on an active region over the p-well, and a p.sup.+ layer is formed by injecting impurities. After above processes a gate poly 35 and a source-drain region for transistors are formed, and a contact is formed to form a storage poly 41, and said storage poly is etched selectively.
Thereafter, an insulating layer 46 for a capacitor is formed by oxidizing said storage poly, and a plate poly 48 is deposited. The layers of an oxide 49, a polycide 50, a B-PSG 51 and a metal 52 are formed in sequence, now the series of processes for manufacturing a DRAM cell are completed.
The effective area of a capacitor 41 of a DRAM cell manufactured by the above described way is determined by the top and side area of the storage poly. To increase the effective area of the stacked capacitor, the thickness of the storage poly 41 is increased up to now.
However, the magnitude of the capacitance manufactured by way of increasing the side area is not sufficient for high-density memories because the cell area of a 4M DRAM is 10 .mu.m.sup.2, but that of a 16M DRAM reduces to 5 .mu.m.sup.2. The increment of thickness of the storage poly in the entire area of the cell causes the deterioration of cell topology so that the patterning of the storage poly and the bit-line and the metal is difficult. The manufacturing of the high-density DRAMS beyond 4M DRAM is difficult by the conventional technology. The reason is that the capacitance per unit cell reduces remarkably when the 16M DRAM is manufactured by the prior technology.